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general description the max7300 compact, serial-interfaced, i/o expan- sion peripheral provides microprocessors with up to 28 ports. each port is individually user configurable to either a logic input or logic output. each port can be configured as either a push-pull logic output capable of sinking 10ma and sourcing 4.5ma, or a schmitt logic input with optional internal pullup. seven ports feature configurable transition detection logic, which generates an interrupt upon change of port logic level. the max7300 is controlled through an i 2 c-compatible 2- wire serial interface, and uses four-level logic to allow 16 i 2 c addresses from only two select pins. the max7300aax and max7300atl have 28 ports and are available in 36-pin ssop and 40-pin tqfn pack- ages, respectively. the max7300aai and MAX7300ATI have 20 ports and are available in 28-pin ssop and tqfn packages. for an spi-interfaced version, refer to the max7301 data sheet. for a pin-compatible port expander with additional 24ma constant-current led drive capability, refer to the max6956 data sheet. applications white goods industrial controllers automotive system monitoring features 400kbps i 2 c-compatible serial interface 2.5v to 5.5v operation -40c to +125c temperature range 20 or 28 i/o ports, each configurable as push-pull logic output schmitt logic input schmitt logic input with internal pullup 11 a (max) shutdown current logic transition detection for seven i/o ports max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ________________________________________________________________ maxim integrated products 1 19-2413; rev 7; 9/11 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ordering information part temp range pin-package max7300aai -40 c to +125 c 28 ssop MAX7300ATI -40 c to +125 c 28 tqfn-ep* max7300aax -40 c to +125 c 36 ssop max7300atl -40 c to +125 c 40 tqfn-ep* p5 p4 p7 p8 p6 p10 p9 p12 p13 p11 p15 p14 p17 p18 p16 p20 p19 i/o 5 i/o 4 i/o 7 i/o 8 i/o 6 i/o 10 i/o 9 i/o 12 i/o 13 i/o 11 i/o 15 i/o 14 i/o 17 i/o 18 i/o 16 i/o 20 i/o 19 i/o 21 i/o 22 i/o 23 p22 p23 p21 36 2 3 4 33 35 34 29 27 31 24 25 22 21 23 v+ gnd gnd ad0 ad1 scl p30 p29 p31 p27 p28 p25 p24 p26 32 30 26 5 7 9 28 6 8 11 10 12 14 15 13 17 16 19 20 18 sda max7300aax 3v data clock i/o 24 i/o 25 i/o 27 i/o 26 i/o 29 i/o 30 i/o 28 i/o 31 47nf 39k ? 1 iset typical operating circuit 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v+ ad1 scl sda p31 p30 p22 p29 p28 p27 p26 p25 p24 p23 p21 p20 p19 p18 p17 p16 p15 p14 p13 p12 ad0 gnd gnd iset 28 ssop top view max7300 pin configurations pin configurations continued at end of data sheet. * ep = exposed pad. devices are also available in a lead(pb)-free/rohs-compliant pack- age. specify lead-free by adding "+" to the part number when order- ing. devices are also available in tape-and-reel packaging. specify tape and reel by adding "t" to the part number when ordering.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +6v scl, sda, ad0, ad1................................................-0.3v to +6v all other pins................................................-0.3v to (v+ + 0.3v) p4?31 current ................................................................?0ma gnd current .....................................................................800ma continuous power dissipation (t a = +70?) 28-pin ssop (derate 9.1mw/? above +70?) ...........727mw 28-pin tqfn (derate 21.3mw/? above +70?) .......1702mw 36-pin ssop (derate 11.8mw/? above +70?) .........941mw 40-pin tqfn (derate 26.3mw/? above t a = +70c).2105mw operating temperature range (t min to t max ) ...............................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? soldering temperature (reflow) lead (pb)-free packages..............................................+260? packages containing lead (pb).....................................+240? electrical characteristics ( typical operating circuit , v v+ = 2.5v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ 2.5 5.5 v t a = +25? 5.5 8 t a = -40? to +85? 10 shutdown supply current i shdn all digital inputs at v+ or gnd t min to t max 11 ? t a = +25? 180 240 t a = -40? to +85? 260 operating supply current i gpoh all ports programmed as outputs high, no load, all other inputs at v+ or gnd t min to t max 280 ? t a = +25? 170 210 t a = -40? to +85? 230 operating supply current i gpol all ports programmed as outputs low, no load, all other inputs at v+ or gnd t min to t max 240 ? t a = +25? 110 135 t a = -40? to +85? 140 operating supply current i gpi all ports programmed as inputs without pullup, ports, and all other inputs at v+ or gnd t min to t max 145 ? inputs and outputs logic high input voltage port inputs v ih 0.7 x v+ v logic low input voltage port inputs v il 0.3 x v+ v input leakage current i ih , i il gpio inputs without pullup, v port = v+ to gnd -100 ? +100 na v v+ = 2.5v 12 19 30 gpio input internal pullup to v+ i pu v v+ = 5.5v 80 120 180 ? hysteresis voltage gpio inputs ? v i 0.3 v
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander _______________________________________________________________________________________ 3 electrical characteristics (continued) ( typical operating circuit , v v+ = 2.5v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units gpio outputs, i source = 2ma, t a = -40? to +85? v+ - 0.7 output high voltage v oh gpio outputs, i source = 1ma, t a = t min to t max (note 2) v+ - 0.7 v port sink current i ol v port = 0.6v 2 10 18 ma output short-circuit current i olsc port configured output low, shorted to v+ 2.75 11 20 ma input high-voltage sda, scl, ad0, ad1 v ih 0.7 x v+ v input low-voltage sda, scl, ad0, ad1 v il 0.3 x v+ v input leakage current sda, scl i ih , i il -50 +50 na input capacitance (note 2) 10 pf output low-voltage sda v ol i sink = 6ma 0.4 v timing characteristics (figure 2) (v v+ = 2.5v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 ? hold time (repeated) start condition t hd , sta 0.6 ? repeated start condition setup time t su , sta 0.6 ? stop condition setup time t su , sto 0.6 ? data hold time t hd , dat (note 3) 15 900 ns data setup time t su , dat 100 ns scl clock low period t low 1.3 ? scl clock high period t high 0.7 ? rise time of both sda and scl signals, receiving t r (notes 2, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 2, 4) 20 + 0.1c b 300 ns fall time of sda transmitting t f , tx (notes 2, 5) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (notes 2, 6) 0 50 ns capacitive load for each bus line c b (note 2) 400 pf
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 4 _______________________________________________________________________________________ shutdown supply current vs. temperature max7300 toc02 temperature ( c) supply current ( a) 97.5 70.0 42.5 15.0 -12.5 4 5 6 7 8 3 -40.0 125.0 v v+ = 5.5v v v+ = 3.3v v v+ = 2.5v operating supply current vs. v+ (outputs unloaded) max7300 toc03 v+ (v) supply current ( ma) 5.0 4.5 4.0 3.5 3.0 2.5 1 0.1 2.0 5.5 all ports output (1) all ports input (pullups disabled) all ports output (0) operating supply current vs. temperature max7300 toc01 temperature ( c) supply current (ma) 97.5 70.0 42.5 15.0 -12.5 0.04 0.08 0.12 0.16 0.20 0.24 0.28 0.32 0.36 0.40 0 -40.0 125.0 v v+ = 2.5v to 5.5v no load all ports output (1) all ports output (0) all ports input high __________________________________________typical operating characteristics (r iset = 39k ? , t a = +25?, unless otherwise noted.) timing characteristics (figure 2) (continued) (v v+ = 2.5v to 5.5v, t a = t min to t max , unless otherwise noted.) (note 1) note 1: all parameters tested at t a = +25?. specifications over temperature are guaranteed by design. note 2: guaranteed by design. note 3: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) in order to bridge the undefined region of scl? falling edge. note 4: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 5: i sink 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 6: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander _______________________________________________________________________________________ 5 gpo source current vs. temperature (output = 1) max7300 toc05 temperature ( c) port source current (ma) 97.5 70.0 42.5 15.0 -12.5 3 4 5 6 7 8 9 2 -40.0 125.0 v port = 1.4v v v+ = 5.5v v v+ = 3.3v v v+ = 2.5v gpo sink current vs. temperature (output = 0) max7300 toc04 temperature ( c) port sink current (ma) 97.5 70.0 -12.5 15.0 42.5 4 6 8 10 12 14 16 18 2 -40.0 125.0 v v+ = 2.5v to 5.5v, v port = 0.6v gpi pullup current vs. temperature max7300 toc06 temperature ( c) pullup current ( a) 97.5 70.0 42.5 15.0 -12.5 100 1000 10 -40.0 125.0 v v+ = 5.5v v v+ = 3.3v v v+ = 2.5v gpo short-circuit current vs. temperature max7300 toc07 temperature ( c) port current (ma) 97.5 70.0 42.5 15.0 -12.5 10 100 1 -40.0 125.0 gpo = 0, port shorted to v+ gpo = 1, port shorted to gnd typical operating characteristics (continued) (r iset = 39k ? , t a = +25?, unless otherwise noted.)
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 6 _______________________________________________________________________________________ detailed description the max7300 general-purpose input/output (gpio) peripheral provides up to 28 i/o ports, p4 to p31, con- trolled through an i 2 c-compatible serial interface. the ports can be configured to any combination of logic inputs and logic outputs, and default to logic inputs on power-up. figure 1 is the max7300 functional diagram. any i/o port can be configured as a push-pull output (sinking 10ma, sourcing 4.5ma), or a schmitt-trigger logic input. each input has an individually selectable internal pullup resis- tor. additionally, transition detection allows seven ports (p24 to p30) to be monitored in any maskable combina- tion for changes in their logic status. a detected transi- tion is flagged through a status register bit, as well as an interrupt pin (port p31), if desired. the port configuration registers individually set the 28 ports, p4 to p31, as gpio. a pair of bits in registers 0x09 through 0x0f sets each port? configuration (tables 1 and 2). the 36-pin max7300aax and 40-pin max7300atl have 28 ports, p4 to p31. the 28-pin max7300ani, max7300aai, and MAX7300ATI have only 20 ports avail- able, p12 to p31. the eight unused ports should be configured as outputs on power-up by writing 0x55 to registers 0x09 and 0x0a. if this is not done, the eight unused ports remain as unconnected inputs and quies- cent supply current rises, although there is no damage to the part. register control of i/o ports across multiple drivers the max7300 offers 20 or 28 i/o ports, depending on package choice. two addressing methods are avail- able. any single port (bit) can be written (set/cleared) at once; or, any sequence of eight ports can be written (set/cleared) in any combination at once. there are no boundaries; it is equally acceptable to write p0 to p7, p1 to p8, or p31 to p38 (p32 to p38 are nonexistent, so the instructions to these bits are ignored). shutdown when the max7300 is in shutdown mode, all ports are forced to inputs, and the pullup current sources are turned off. data in the port and control registers remain unaltered, so port configuration and output levels are restored when the max7300 is taken out of shutdown. the max7300 can still be programmed while in shut- down mode. for minimum supply current in shutdown mode, logic inputs should be at gnd or v+ potential. shutdown mode is exited by setting the s bit in the con- figuration register (table 8). pin 28 ssop 28 tqfn-ep 36 ssop 40 tqfn-ep name function 1 26 1 36 iset bias current setting. connect iset to gnd through a resistor (r iset ) value of 39k ? to 120k ? . 2, 3 27, 28 2, 3 37, 38, 39 gnd ground 4 1 4 40 ad0 ad d r ess inp ut 0. s ets d evi ce sl ave ad d r ess. c onnect to ei ther g n d , v + , s c l, s d a to g i ve four l og i c com b i nati ons. s ee tab l e 3. 5?4 2?1 p 12p 31 i/o p or ts. p 12 to p 31 can b e confi g ur ed as p ush- p ul l outp uts, c m o s - l og i c i np uts, or c m o s - l og i c i np uts w i th w eak p ul l up r esi stor . 5?2 1?0, 12?9, 21?0 p4?31 i/o p or ts. p 4 to p 31 can b e confi g ur ed as p ush- p ul l outp uts, c m o s - l og i c i np uts, or c m o s - l og i c i np uts w i th w eak p ul l up r esi stor . 11, 20, 31 n.c. no connection. not internally connected. 25 22 33 32 sda i 2 c-compatible serial-data i/o 26 23 34 33 scl i 2 c-compatible serial-clock input 27 24 35 34 ad1 ad d r ess inp ut 1. s ets d evi ce sl ave ad d r ess. c onnect to ei ther g n d , v + , s c l, s d a to g i ve four l og i c com b i nati ons. s ee tab l e 3. 28 25 36 35 v+ positive supply voltage. bypass v+ to gnd with minimum 0.047? capacitor. ep exposed pad (tqfn only). ep is internally connected to gnd. connect to a large ground plane to maximize thermal performance. not intended as an electrical connection point. pin description
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander _______________________________________________________________________________________ 7 serial interface serial addressing the max7300 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the max7300, and generates the scl clock that synchronizes the data transfer (figure 2). the max7300 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on sda. the max7300 scl line operates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2- wire interface, or if the master in a single-master system has an open-drain scl output. each transmission consists of a start condition (figure 3) sent by a master, followed by the max7300 7-bit slave address plus r/ w bit (figure 6), a register address byte, one or more data bytes, and finally a stop condition (figure 3). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning sda from low to high while scl is high. the bus is then free for another transmission (figure 3). bit transfer one data bit is transferred during each clock pulse. the data on sda must remain stable while scl is high (figure 4). acknowledge the acknowledge bit is a clocked 9th bit, which the recipient uses to handshake receipt of each byte of data (figure 5). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is sta- ble low during the high period of the clock pulse. when the master is transmitting to the max7300, the max7300 generates the acknowledge bit since the table 1. port configuration map register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 port configuration for p7, p6, p5, p4 0x09 p7 p6 p5 p4 port configuration for p11, p10, p9, p8 0x0a p11 p10 p9 p8 port configuration for p15, p14, p13, p12 0x0b p15 p14 p13 p12 port configuration for p19, p18, p17, p16 0x0c p19 p18 p17 p16 port configuration for p23, p22, p21, p20 0x0d p23 p22 p21 p20 port configuration for p27, p26, p25, p24 0x0e p27 p26 p25 p24 port configuration for p31, p30, p29, p28 0x0f p31 p30 p29 p28 table 2. port configuration matrix port configuration bit pair mode function port register (0x20?x5f) pin behavior address code ( hex ) upper lower do not use this setting 0x09 to 0x0f 0 0 register bit = 0 active-low logic output output gpio output register bit = 1 active-high logic output 0x09 to 0x0f 0 1 input gpio input without pullup schmitt logic input 0x09 to 0x0f 1 0 input gpio input with pullup register bit = input logic level schmitt logic input with pullup 0x09 to 0x0f 1 1
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 8 _______________________________________________________________________________________ max7300 is the recipient. when the max7300 is trans- mitting to the master, the master generates the acknowledge bit since the master is the recipient. slave address the max7300 has a 7-bit-long slave address (figure 6). the eighth bit following the 7-bit slave address is the r/ w bit. it is low for a write command and high for a read command. the first 3 bits (msbs) of the max7300 slave address are always 100. slave address bits a3, a2, a1, and a0 are selected by the address inputs, ad1 and ad0. these two input pins can be connected to gnd, v+, sda, or scl. the max7300 has 16 possible slave addresses (table 3), and therefore a maximum of 16 max7300 devices can share the same interface. message format for writing the max7300 a write to the max7300 comprises the transmission of the max7300? slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte. the com- mand byte determines which register of the max7300 is to be written by the next byte, if received. if a stop condition is detected after the command byte is received, then the max7300 takes no further action (figure 7) beyond storing the command byte. slave address byte d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 r/w 8 8 ce data 8 sda scl port registers gpio configuration p4 to p31 address matcher ad0 ad1 command byte data byte r/w 7-bit device address 7 7 to command registers to/from data registers gpio data r/w configuration registers port change detector mask register command register decode 8 data byte command byte figure 1. max7300 functional diagram
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander _______________________________________________________________________________________ 9 any bytes received after the command byte are consid- ered data bytes. the first data byte goes into the inter- nal register of the max7300 selected by the command byte (figure 8). if multiple data bytes are transmitted before a stop condition is detected, these bytes are generally stored in subsequent max7300 internal regis- ters because the command byte address generally autoincrements (table 4). message format for reading the max7300 is read using the max7300? internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for a write. the pointer generally autoincrements after each data byte is read using the same rules as for a write (table 4). thus, a read is initiated by first configuring the max7300? command byte by performing a write (figure 7). the master can now read ??consecutive bytes from the max7300, with the first data byte being read from the register addressed by the initialized command byte (figure 9). when performing read-after-write verification, remember to reset the command byte? address because the stored control byte address generally has been autoincremented after the write (table 4). table 5 is the register address map. figure 2. 2-wire serial interface timing details scl sda start condition stop condition repeated start condition start condition t su, dat t hd, dat t low t hd, sta t high t r t f t su, sta t hd, sta t su, sto t buf figure 3. start and stop conditions sda scl s start condition p stop condition sda scl data line stable; data valid change of data allowed figure 4. bit transfer
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 10 ______________________________________________________________________________________ operation with multiple masters if the max7300 is operated on a 2-wire interface with multiple masters, a master reading the max7300 should use a repeated start between the write, which sets the max7300? address pointer, and the read(s) that takes the data from the location(s). this is because it is possi- ble for master 2 to take over the bus after master 1 has set up the max7300? address pointer, but before master 1 has read the data. if master 2 subsequently changes, the max7300? address pointer, then master 1? delayed read can be from an unexpected location. command address autoincrementing address autoincrementing allows the max7300 to be configured with the shortest number of transmissions by minimizing the number of times the command address needs to be sent. the command address stored in the max7300 generally increments after each data byte is written or read (table 4). initial power-up on initial power-up, all control registers are reset and the max7300 enters shutdown mode (table 6). transition (port data change) detection port transition detection allows any combination of the seven ports p24?30 to be continuously monitored for changes in their logic status (figure 10). a detected change is flagged on the transition detection mask reg- ister int status bit, d7 (table 10). if port p31 is config- ured as an output (tables 1 and 2), then p31 also automatically becomes an active-high interrupt output (int), which follows the condition of the int status bit. port p31 is set as output by writing bit d7 = 0 and bit d6 = 1 to the port configuration register (table 1). note that the max7300 does not identify which specific port(s) caused the interrupt, but provides an alert that one or more port levels have changed. the mask register contains 7 mask bits that select which of the seven ports p24?30 are to be monitored (table 10). set the appropriate mask bit to enable that port for transition detect. clear the mask bit if transi- scl sda by transmitter clock pulse for acknowledgment start condition sda by receiver 12 89 s figure 5. acknowledge sda scl 1 0 a3 a2 a1 a0 0 msb lsb r/w ack figure 6. slave address
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ______________________________________________________________________________________ 11 tions on that port are to be ignored. transition detection works regardless of whether the port being monitored is set to input or output, but generally, it is not particularly useful to enable transition detection for outputs. to use transition detection, first set up the mask regis- ter and configure port p31 as an output, as described above. then enable transition detection by setting the m bit in the configuration register (table 9). whenever the configuration register is written with the m bit set, the max7300 updates an internal 7-bit snapshot regis- ter, which holds the comparison copy of the logic states of ports p24 through p30. the update action occurs regardless of the previous state of the m bit, so that it is not necessary to clear the m bit and then set it again to update the snapshot register. when the configuration register is written with the m bit set, transition detection is enabled and remains enabled until either the configuration register is written with the m bit clear, or a transition is detected. the int status bit (transition detection mask register bit d7) goes low. port p31 (if enabled as int output) also goes low, if it was not already low. once transition detection is enabled, the max7300 continuously compares the snapshot register against the changing states of p24 through p31. if a change on any of the monitored ports is detected, even for a short time (like a pulse), the int status bit (transition detec- tion mask register bit d7) is set. port p31 (if enabled as int output) also goes high. the int output and int sta- tus bit are not cleared if more changes occur or if the data pattern returns to its original snapshot condition. the only way to clear int is to access (read or write) the transition detection mask register (table 10). so if the transition detection mask register is read twice in succession after a transition event, the first time reads with bit d7 set (identifying the event), and the second time reads with bit d7 clear. transition detection is a one-shot event. when int has been cleared after responding to a transition event, tran- sition detection is automatically disabled, even though the m bit in the configuration register remains set (unless cleared by the user). reenable transition detection by writing the configuration register with the m bit set to take a new snapshot of the seven ports p24 to p30. external component r iset the max7300 uses an external resistor, r iset, to set internal biasing. use a resistor value of 39k ? . applications information low-voltage operation the max7300 operates down to 2v supply voltage (although the sourcing and sinking currents are not guar- anteed), providing that the max7300 is powered up ini- tially to at least 2.5v to trigger the device? internal reset. serial interface latency when a max7300 register is written through the i 2 c interface, the register is updated on the rising edge of scl during the data byte? acknowledge bit (figure 5). the delay from the rising edge of scl to the internal register being updated can range from 50ns to 350ns. saap 0 slave address command byte acknowledge from max7300 r/w acknowledge from max7300 d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition figure 7. command byte received saaap 0 slave address command byte data byte acknowledge from max7300 1 byte autoincrement memory word address d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how command byte and data byte map into max7300s register acknowledge from max7300 acknowledge from max7300 r/w figure 8. command and single data byte received
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 12 ______________________________________________________________________________________ command byte address range autoincrement behavior x0000000 to x1111110 command address autoincrements after byte read or written x1111111 command address remains at x1111111 after byte written or read pin connection device address ad1 ad0 a6 a5 a4 a3 a2 a1 a0 gnd gnd 1 0 0 0 0 0 0 gnd v+ 1000001 gnd sda 1000010 gnd scl 1000011 v+ gnd 1000100 v+ v+ 1000101 v+ sda 1000110 v+ scl 1000111 sda gnd 1001000 sda v+ 1001001 sda sda 1 0 0 1 0 1 0 sda scl 1 0 0 1 0 1 1 scl gnd 1001100 scl v+ 1001101 scl sda 1 0 0 1 1 1 0 scl scl 1 0 0 1 1 1 1 sa aap 0 slave address command byte data byte acknowledge from max7300 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how command byte and data byte map into max7300s register acknowledge from max7300 r/w ??bytes autoincrement memory word address acknowledge from max7300 figure 9. ??data bytes received table 3. max7300 address map table 4. autoincrement rules pc board layout considerations ensure that all the max7300 gnd connections are used. for tqfn versions, connect the underside exposed pad to gnd. a ground plane is not necessary, but may be useful to reduce supply impedance if the max7300 outputs are to be heavily loaded. keep the track length from the iset pin to the r iset resistor as short as possible, and take the gnd end of the register either to the ground plane or directly to the gnd pins. power-supply considerations the max7300 operates with power-supply voltages of 2.5v to 5.5v. bypass the power supply to gnd with a 0.047? capacitor as close to the device as possible. add a 1? capacitor if the max7300 is far away from the board? input bulk decoupling capacitor.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ______________________________________________________________________________________ 13 table 5. register address map command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code no-op x 0 0 0 0 0 0 0 0x00 configuration x 0 0 0 0 1 0 0 0x04 transition detect mask x 0 0 0 0 1 1 0 0x06 factory reserved; do not write to this port x 0 0 0 0 1 1 1 0x07 port configuration p7, p6, p5, p4 x 0 0 0 1 0 0 1 0x09 port configuration p11, p10, p9, p8 x 0 0 0 1 0 1 0 0x0a port configuration p15, p14, p13, p12 x 0 0 0 1 0 1 1 0x0b port configuration p19, p18, p17, p16 x 0 0 0 1 1 0 0 0x0c port configuration p23, p22, p21, p20 x 0 0 0 1 1 0 1 0x0d port configuration p27, p26, p25, p24 x 0 0 0 1 1 1 0 0x0e port configuration p31, p30, p29, p28 x 0 0 0 1 1 1 1 0x0f port 0 only (virtual port, no action) x 0 1 0 0 0 0 0 0x20 port 1 only (virtual port, no action) x 0 1 0 0 0 0 1 0x21 port 2 only (virtual port, no action) x 0 1 0 0 0 1 0 0x22 port 3 only (virtual port, no action) x 0 1 0 0 0 1 1 0x23 port 4 only (data bit d0. d7-d1 read as 0) x 0 1 0 0 1 0 0 0x24 port 5 only (data bit d0. d7-d1 read as 0) x 0 1 0 0 1 0 1 0x25 port 6 only (data bit d0. d7-d1 read as 0) x 0 1 0 0 1 1 0 0x26 port 7 only (data bit d0. d7-d1 read as 0) x 0 1 0 0 1 1 1 0x27 port 8 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 0 0 0 0x28 port 9 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 0 0 1 0x29 port 10 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 0 1 0 0x2a port 11 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 0 1 1 0x2b port 12 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 1 0 0 0x2c port 13 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 1 0 1 0x2d port 14 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 1 1 0 0x2e port 15 only (data bit d0. d7-d1 read as 0) x 0 1 0 1 1 1 1 0x2f port 16 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 0 0 0 0x30 port 17 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 0 0 1 0x31 port 18 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 0 1 0 0x32 port 19 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 0 1 1 0x33 port 20 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 1 0 0 0x34 port 21 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 1 0 1 0x35 port 22 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 1 1 0 0x36 port 23 only (data bit d0. d7-d1 read as 0) x 0 1 1 0 1 1 1 0x37 port 24 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 0 0 0 0x38 port 25 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 0 0 1 0x39
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 14 ______________________________________________________________________________________ command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code port 26 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 0 1 0 0x3a port 27 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 0 1 1 0x3b port 28 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 1 0 0 0x3c port 29 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 1 0 1 0x3d port 30 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 1 1 0 0x3e port 31 only (data bit d0. d7-d1 read as 0) x 0 1 1 1 1 1 1 0x3f 4 ports 4? (data bits d0?3. d4?7 read as 0) x 1 0 0 0 0 0 0 0x40 5 ports 4? (data bits d0?4. d5?7 read as 0) x 1 0 0 0 0 0 1 0x41 6 ports 4? (data bits d0?5. d6?7 read as 0) x 1 0 0 0 0 1 0 0x42 7 ports 4?0 (data bits d0?6. d7 reads as 0) x 1 0 0 0 0 1 1 0x43 8 ports 4?1 (data bits d0?7) x 1 0 0 0 1 0 0 0x44 8 ports 5?2 (data bits d0?7) x 1 0 0 0 1 0 1 0x45 8 ports 6?3 (data bits d0?7) x 1 0 0 0 1 1 0 0x46 8 ports 7?4 (data bits d0?7) x 1 0 0 0 1 1 1 0x47 8 ports 8?5 (data bits d0?7) x 1 0 0 1 0 0 0 0x48 8 ports 9?6 (data bits d0?7) x 1 0 0 1 0 0 1 0x49 8 ports 10?7 (data bits d0?7) x 1 0 0 1 0 1 0 0x4a 8 ports 11?8 (data bits d0?7) x 1 0 0 1 0 1 1 0x4b 8 ports 12?9 (data bits d0?7) x 1 0 0 1 1 0 0 0x4c 8 ports 13?0 (data bits d0?7) x 1 0 0 1 1 0 1 0x4d 8 ports 14?1 (data bits d0?7) x 1 0 0 1 1 1 0 0x4e 8 ports 15?2 (data bits d0?7) x 1 0 0 1 1 1 1 0x4f 8 ports 16?3 (data bits d0?7) x 1 0 1 0 0 0 0 0x50 8 ports 17?4 (data bits d0?7) x 1 0 1 0 0 0 1 0x51 8 ports 18?5 (data bits d0?7) x 1 0 1 0 0 1 0 0x52 8 ports 19?6 (data bits d0?7) x 1 0 1 0 0 1 1 0x53 8 ports 20?7 (data bits d0?7) x 1 0 1 0 1 0 0 0x54 8 ports 21?8 (data bits d0?7) x 1 0 1 0 1 0 1 0x55 8 ports 22?9 (data bits d0?7) x 1 0 1 0 1 1 0 0x56 8 ports 23?0 (data bits d0?7) x 1 0 1 0 1 1 1 0x57 8 ports 24?1 (data bits d0?7) x 1 0 1 1 0 0 0 0x58 7 ports 25?1 (data bits d0?6. d7 reads as 0) x 1 0 1 1 0 0 1 0x59 6 ports 26?1 (data bits d0?5. d6?7 read as 0) x 1 0 1 1 0 1 0 0x5a 5 ports 27?1 (data bits d0?4. d5?7 read as 0) x 1 0 1 1 0 1 1 0x5b 4 ports 28?1 (data bits d0?3. d4?7 read as 0) x 1 0 1 1 1 0 0 0x5c 3 ports 29?1 (data bits d0?2. d3?7 read as 0) x 1 0 1 1 1 0 1 0x5d 2 ports 30?1 (data bits d0?1. d2?7 read as 0) x 1 0 1 1 1 1 0 0x5e 1 port 31 only (data bits d0. d1?7 read as 0) x 1 0 1 1 1 1 1 0x5f table 5. register address map (continued) note: unused bits read as zero.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ______________________________________________________________________________________ 15 table 6. power-up configuration register data register function power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 port register bits 4 to 31 gpio output low 0x24 to 0x3f xxxxxxx0 configuration register shutdown enabled transition detection disabled 0x04 0 0 x x x x x 0 input mask register all clear (masked off) 0x06 x 0 0 0 0 0 0 0 port configuration p7, p6, p5, p4: gpio inputs without pullup 0x09 1 0 1 0 1 0 1 0 port configuration p11, p10, p9, p8: gpio inputs without pullup 0x0a 1 0 1 0 1 0 1 0 port configuration p15, p14, p13, p12: gpio inputs without pullup 0x0b 1 0 1 0 1 0 1 0 port configuration p19, p18, p17, p16: gpio inputs without pullup 0x0c 1 0 1 0 1 0 1 0 port configuration p23, p22, p21, p20: gpio inputs without pullup 0x0d 1 0 1 0 1 0 1 0 port configuration p27, p26, p25, p24: gpio inputs without pullup 0x0e 1 0 1 0 1 0 1 0 port configuration p31, p30, p29, p28: gpio inputs without pullup 0x0f 1 0 1 0 1 0 1 0 x = unused bits; if read, zero results.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 16 ______________________________________________________________________________________ table 7. configuration register format register data function address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 configuration register 0x04 m 0 xxxxxs table 8. shutdown control (s data bit d0) format register data function address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 shutdown 0x04 m 0 xxxxx0 normal operation 0x04 m 0 xxxxx1 table 9. transition detection control (m data bit d7) format register data function address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 disabled 0x04 0 0 xxxxxs enabled 0x04 1 0 xxxxxs table 10. transition detection mask register register data function register address (hex) read/ write d7 d6 d5 d4 d3 d2 d1 d0 read int status* mask register 0x06 write unchanged port 30 mask port 29 mask port 28 mask port 27 mask port 26 mask port 25 mask port 24 mask * int is automatically cleared after it is read.
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ______________________________________________________________________________________ 17 gpio input conditioning p31 p30 p29 p28 p27 p26 p25 p24 gpio/port output latch gpio input conditioning gpio/port output latch gpio input conditioning gpio/port output latch gpio input conditioning gpio/port output latch gpio input conditioning gpio/port output latch gpio input conditioning gpio/port output latch gpio input conditioning gpio/port output latch d q d q d q d q d q d q d q clock pulse when writing configuration register with m bit set or configuration register m bit = 1 r s gpio in gpio/port out clock pulse after each read access to mask register int status stored as msb of mask register mask register bit 6 mask register bit 5 mask register bit 4 mask register bit 3 mask register bit 2 mask register bit 1 mask register lsb gpio in gpio/port out gpio in gpio/port out gpio in gpio/port out gpio in gpio/port out gpio in gpio/port out gpio in gpio/port out gpio in gpio/port out gpio input conditioning gpio/port output latch int output latch figure 10. maskable gpio ports p24 to p31
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander 18 ______________________________________________________________________________________ top view 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v+ ad1 scl sda p4 p31 p26 p5 p30 p6 p29 p7 p28 p27 p17 p16 p15 p11 p14 p10 p13 p9 p12 p8 ad0 gnd gnd iset 36 ssop max7300 22 21 20 19 15 16 17 18 p22 p25 p24 p23 p21 p20 p19 p18 max7300 max7300 p4 p31 p30 p6 p28 p27 p26 p29 p7 p5 p9 p13 p10 p14 p11 p15 p16 p17 p12 p8 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 p21 p22 p23 p25 n.c. p20 p19 p18 n.c. 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 gnd gnd gnd iset v+ ad1 scl sda n.c. ad0 40 tqfn-ep p24 28 27 26 25 24 23 22 gnd gnd iset v+ ad1 scl sda 8 9 10 11 12 13 14 p18 p19 p20 p21 p22 p23 p24 15 16 17 18 19 20 21 p25 p26 p27 p28 p29 p30 p31 7 6 5 4 3 2 1 p17 p16 p15 p14 p13 p12 ado 28 tqfn-ep top view pin configurations (continued)
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander ______________________________________________________________________________________ 19 chip information process: cmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 28 ssop a28+1 21-0056 90-0095 28 tqfn-ep t2855+6 21-0140 90-0026 36 ssop a36+4 21-0040 90-0098 40 tqfn-ep t4066+5 21-0141 90-0055
max7300 2-wire-interfaced, 2.5v to 5.5v, 20-port or 28-port i/o expander maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidanc e. 20 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 1 9/11 updated ordering information , absolute maximum ratings , pin description , table 1 , and package information sections 1, 2, 6, 7, 19

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